Scan path is a type of analysis well-known for checking whether one or more functional blocks of an integrated circuit is operating correctly.
It is based on the use of serial-type scanning signals which operate on chains of scanning cells (latches) located at the input and output of individual functional blocks with a function of stimulation and assessment, respectively, of the operational state of the same functional blocks.
In this way it is possible to progressively update the operational state of the functional block under examination and to correspondingly obtain at output a signal indicative of the various operational states assumed by the same functional block with each inquiry of the serial signal at input.
In this respect it should be noted that a device such as a microprocessor is constituted to a large extent by a clocked sequential logic, that is, operating at a fixed rate set by a clock signal. It is thus easy to identify functional blocks whose input and output signals are clocked, that is, are controlled by a clock signal.
It appears evident that, if the clocking phase of the inputs of said functional blocks is lengthened to allow by means of serial scanning the alteration of some or all of the same inputs, nothing is damaged. This hypothesis is naturally valid as long as the logic is static.
In the case of a generic functional block made with a static logic it is possible to define the "stimulation phase" as the phase wherein the inputs are memorized and the "assessment phase" as the phase wherein the outputs of the functional block are stored in outputs cells or latches.
It is also possible to say in general that the alteration requested by a scan path analysis with respect to the original logic is represented by the addition of scanning or latch cells at each input and output, connecting the inserted one to the pre-existing one so as to maintain the old function, that is memorizing in parallel the input signal coming from the normal functional path or receiving and memorizing the serial inputs coming from an external path.
Each scanning cell (latch) consists of a master part and of a slave part, which are clocked on opposite phases of a scanning clock. The scanning cell stores the new data presented at input and presents the previously stored data at output, respectively.
In the known devices, the two phases of the scanning clock are generated at the input of the integrated circuit and must propagate through many gates, until they reach the cells concerned. Because of the different time delays in the transistors, this involves the risk of an overlap of the two phases, especially in the case of very long paths, with the consequent possible charging of the master part with the slave part still open and the consequent possible immediate loss of the new content introduced into the master part.